Create Once and Test Everywhere: The Promise of Portable Stimulus


The issue was easy: Totally different take a look at platforms have been utilized by totally different engineering professionals all through the verification phases of simulation, emulation, prototyping and different kinds of testing. Within the semiconductor chip world, verification refers back to the course of wherein a design is examined (or verified) in opposition to a given design specification earlier than tape-out, i.e., earlier than the design is made right into a silicon chip.

The answer appeared easy: Create a high-level take a look at atmosphere which could possibly be reused on these totally different platforms and at totally different occasions all through the verification course of.

The fact was something however easy. To begin with, every verification exercise needed to fulfill a special set of necessities. Additional, every verification platform used totally different languages and approaches particular to the side of the system that have been being  are attempting examined. It wasn’t straightforward to reuse verification necessities from one platform to a different.

That’s why the Accellera Moveable Stimulus Customary (PSS) was developed again in 2017. The usual’s objective was to specify the take a look at intent in an summary approach that could possibly be mapped to totally different necessities on totally different platforms. Thus, a single specification could possibly be developed into take a look at suites after which utilized by many various folks and deployed to many various environments. On this approach, {hardware} chip designers via embedded software program programmers may deploy take a look at and verification suites throughout many various take a look at environments.

At this time, many chip builders depend on SystemVerilog to do each design and verification of chip techniques. Formally, SystemVerilog is each a textual {hardware} description language (HDL) and a {hardware} verification language (HDL).

And therein was the problem. SystemVerilog is nice as a language used to create {hardware} checkers and testbenches. However it isn’t properly suited to reuse the stimulus code on the software program system degree. At this excessive degree of abstraction, exams are typically executed on embedded processors contained in the design the place machine code or C-code directions have entry to working system providers.

To assist deal with these {hardware} and software program coding variations, the Accellera normal outlined two languages for creating transportable stimulus. One is a customized domain-specific language (DSL) that makes use of a construction not dissimilar to that of Python. The opposite is a category library for C++ that permits a use extra acquainted to software program builders – an analogous strategy to that used for SystemC.

“Moveable Stimulus permits for reuse throughout varied platforms and throughout chip hierarchy,” explains Lu Dai, Chairman of Accellera. “An SoC design can write a take a look at utilizing PS which, via a software circulation, will generate the C language-based take a look at. That native take a look at can then be reused from pre-Silicon verification to emulation and even to post-Silicon software program bring-up.

Dai went on to say that reuse throughout the hierarchy – from IP blocks to the complete SOC verification – was tougher as a result of software distributors don’t but simply assist that software circulation.

The most recent model of the Moveable Stimuls Customary (PSS) was the topic of a lot dialogue on the latest Design-Verification Convention (DVCon) 2020. Amongst different issues, it was announcement that the subsequent model, PSS 1.1, would  obtainable for public assessment by the second half of 2020. This model will embody modeling enhancements, higher take a look at realization and enhancements for the verification programmer.

Picture Supply: Accellera

John Blyler is a Design Information senior editor, masking the electronics and superior manufacturing areas. With a BS in Engineering Physics and an MS in Electrical Engineering, he has years of hardware-software-network techniques expertise as an editor and engineer inside the superior manufacturing, IoT and semiconductor industries. John has co-authored books associated to system engineering and electronics for IEEE, Wiley, and Elsevier.

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